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(R)
STV9937
120-MHz On-Screen Display for Monitors including PictureBooSTTM and 4 True Independent Window Displays
DATASHEET
Main Features
Horizontal frequency up to 150 kHz IC interface for microcontrollers with slave address BA(h) in Read and Write modes
PictureBoosta
Pixel clock (FPIXEL1) for the PictureBooSTa (PB) from 30 to 60 MHz synchronised either on Hsync or on Hfly: CLK1 Window position programmable by RGB or I2C interface Video Analog inputs with comparator on three channels Three 8 bit registers for other data, programmable by RGB
PDIP 24 (Plastic Dual In line Shrink Package) ORDER CODE: STV9937P/AA
496 standard and 16 multi-color characters or graphic fonts in ROM. Character fonts can be customized using a mask-programmable ROM Characters
OSD
On-chip Pixel Clock Generator (FPIXEL2) from 7.68 MHz to 120 MHz, CLK2 OSD clock synchronized on Hsync or Hfly Programmable horizontal resolutions from 384 to 1524 dots per scan line 4 independent windows all with character display Overlapping windows with automatic control of display priorities and scrolling menu effects Independent and programmable displays, positions and sizes for each window Transparent or 8 programmable background colors for each window Window size up to 16 rows of 32 characters Each window has its own bordering or shadowing effects with programmable color, height and width Each window can be separately erased Programmable common positioning to easily control centered display
Common character height and row space. Character height from 18 to 127 lines and space lines from 0 to 62 split above and below character rows 12 x 18 dot matrix per character Display of up to 640 characters Programmable shadow effects for characters in each separate window 32 programmable background, foreground, blinking character colors for characters (8 possibilities per window) 8 selectable colors for standard characters Transparent and 8 selectable colors for background Fade-in/Fade-out effects Possibility of full-screen display with a selectable color

On-Screen Effects

February 2004
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STV9937 Chapter 1
1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Description ................................................................................................................... 7
Chapter 2
2.1
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6
Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
IC Protocol .......................................................................................................................... 9
Data to Write .........................................................................................................................................................9 Transmission Formats ...........................................................................................................................................9 Format, Window and Row Address (FWR) .........................................................................................................10 Format, Attribute and Column Address (FAC) ....................................................................................................10 Control Data, Color Codes or Character Codes .................................................................................................11 Configuration of Transmission Formats .............................................................................................................11
2.2
Format Changing ............................................................................................................... 11
To change from Format A to Format B ...............................................................................................................11 To change from Format A to Format C ...............................................................................................................11 To change from Format B to Format A ...............................................................................................................11 To change from Format B to Format C ...............................................................................................................12
2.3 2.4
Read Mode ......................................................................................................................... 12 Addressing Map ................................................................................................................. 12
Chapter 3
3.1 3.2
3.2.1 3.2.2
Window Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Enable Display ................................................................................................................... 14 Origin Positions for the 4 Windows .................................................................................... 14
General Horizontal Delay (HD) ...........................................................................................................................14 General Vertical Delay (VD) ................................................................................................................................14
3.3
3.3.1 3.3.2
Window Positions in the Frame .......................................................................................... 15
Window Horizontal Delay ....................................................................................................................................15 Window Vertical Delay ........................................................................................................................................15
3.4
3.4.1 3.4.2
Window Size: Number of Character Rows and Character Columns .................................. 16
Window Horizontal Size ......................................................................................................................................16 Window Vertical Size ..........................................................................................................................................16
3.5 3.6
3.6.1 3.6.2 3.6.3 3.6.4
Window Background Color ................................................................................................. 17 Window Bordering and Shadowing Effects ........................................................................ 17
Enable Bordering or Shadowing Effects .............................................................................................................17 Bordering or Shadowing Selection .....................................................................................................................17 Border or Shadow Color .....................................................................................................................................18 Bordering or Shadowing Size .............................................................................................................................18
3.7
Window Display Priority Management ............................................................................... 19
Chapter 4
4.1 4.2 4.3
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Character Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
General Description ........................................................................................................... 20 Horizontal Resolution ........................................................................................................ 20 Character Height ............................................................................................................... 20
STV9937
4.4 4.5
4.5.1 4.5.2 4.5.3
Space Lines ....................................................................................................................... 21 Character Colors ................................................................................................................ 22
Character Background Color ..............................................................................................................................22 Character Color ...................................................................................................................................................23 Character Blinking Effect ....................................................................................................................................24
4.6 4.7
Character Shadowing ......................................................................................................... 24 Character Font ................................................................................................................... 25
Chapter 5
5.1 5.2 5.3 5.4
RAM Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Character Coding ............................................................................................................... 26 Window Memory Allocation ................................................................................................ 26 Memory Size Allocation ...................................................................................................... 26 Window Reset .................................................................................................................... 28
Chapter 6 Chapter 7
7.1 7.2
7.2.1 7.2.2
Pixel Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Picture BooSTTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Video RGB Input Stage ...................................................................................................... 30 PictureBooSTTM RGB Decoder ........................................................................................ 31
Data Sent Using IC ............................................................................................................................................31 Data Sent Using the RGB Channel ....................................................................................................................31
7.3 7.4 7.5
Control Registers Description ............................................................................................ 33 Line and Pixel Offsets ........................................................................................................ 34 PLL Synchronised .............................................................................................................. 34
Chapter 8
8.1 8.2 8.3 8.4
General OSD Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Enable OSD ....................................................................................................................... 35 Fade-in and Fade-out Effect .............................................................................................. 35 Full Screen Display ............................................................................................................ 35 Signal Polarity and Triggering ........................................................................................... 36
Vertical Sync Triggering (VS input) .....................................................................................................................36 Horizontal Sync Triggering (HSYNC input) .........................................................................................................36 RGB Output Polarity (ROUT, GOUT and BOUT outputs) ...................................................................................36 Fast Blanking Output Polarity (FBLK output) ......................................................................................................37
8.5
Reset .................................................................................................................................. 37
Power On Reset .................................................................................................................................................37 Soft Reset ...........................................................................................................................................................37 PLL Register Reset .............................................................................................................................................37
Chapter 9
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
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STV9937
9.1 Register Specification ........................................................................................................ 38
Chapter 10
10.1
10.1.1 10.1.2
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Software Hints .................................................................................................................... 42
Programming Recommendations .......................................................................................................................42 Examples of Programming ..................................................................................................................................42 Hard reset at power-up (following a power-up) ...................................................................................................42 Change of position & size of 1 window (ex. window 3) without disable of window .............................................42 Re-allocation, reset, and writing new characters in windows ..............................................................................43
10.2
Hardware Hints .................................................................................................................. 43
Chapter 11 Chapter 12
12.1 12.2 12.3 12.4
Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Electrical and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Absolute Maximum Ratings ............................................................................................... 45 Operating Conditions ......................................................................................................... 45 Electrical and Timing Characteristics ................................................................................. 45 IC Bus Characteristics ...................................................................................................... 46
Chapter 13 Chapter 14
Package Mechanical Data
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
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STV9937
General Description
1
General Description
The STV9937 is an Advanced On Screen Display generator for CRT monitors. It includes a specific architecture allowing multiple menu displays, a built in 512 character ROM and the Picture BooSTTM system. The patented Picture BooSTTM feature allows images to be boosted either within a window, a screen area or even over the entire screen. Using traditional architecture (OSD + Preamp STV9212) and without any additional devices on the CRT board, Picture BooSTTM boosts the brightness and sharpness of the video on CRT displays giving a TV like effect. The STV9937 can drive Picture BooSTTM either through the VGA cable (using RGB or DDC), through the USB channel via the MCU or through the OSD menu (the registers can be accessed by the MCU via IC). The STV9937 embeds the RGB data decoder, the Picture BooSTTM Control Registers and the Picture BooSTTM signal generator. Along with the Picture BooSTTM and traditional OSD features, the STV9937 allows a simultaneous display of up to four menus anywhere on the screen. Each of the four independent windows, all displaying characters, can be overlapped and display priorities are automatically controlled.

Window sizes and positions are independently programmable as well as scrolling menu effects. Programming of the general OSD and of the 4 windows is controlled by an IC bus in Read and Write modes, to suit the various CRT displays. Associated with an easily programmable character height, the internal PLL generates the programmable pixel clock, without using a crystal oscillator, that defines the character width making the device suitable for multi-sync applications. A maximum of 640 characters, defined in the mask-programmable ROM, are distributed among the 4 windows and displayed simultaneously.
Figure 1: Multi-window Concept with Character Display
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General Description
Figure 2: STV9937 Block Diagram
STV9937
STV9937
VCO RP
RIN
GIN
BIN
STV9937
OSD Pixel Clock PLL PB Pixel Clock RGB Input Buffer
HSYNC
VS
PB Sequencer
Picture BooSTTM Decoder and Generator
PB
HFLY
OSD Sequencer 4 Windows OSD Generator RAM
SCL SDA
I2C Interface And Registers Reset Signals
ROM
TEST1 Test TEST2 Reset
ROUT
GOUT
BOUT
FBLK
Figure 3: PictureBooSTTM System Block Diagram
Computer main Unit
Monitor CRT board
IP2 SD
PictureBooSTTM Color code
4
Contrast Drive
Video Amplifier AC or DC
Video Card
I2C
Boost gain & Sharpness
DDC H Sync V Sync
PreAmplifier: STV9212
DIP
24
R
G
B
Boost
OSD OSD generator
FBlk H Fly
PictureBooST TM
Decoder Window Coordinate register
Picture booST TM Window TM Software
Line PLL
H Sync
OSD: STV9937
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STV9937
General Description
1.1
Pin Description
Figure 4: Pin Connections
AVSS RP VCO AVDD TEST1 TEST2 HFLY VS HSYNC SDA SCL
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
IVSS BIN GIN RIN IVDD DVDD DVSS PB BOUT GOUT ROUT FBLK
Table 1: Pin Descriptions N
1 2 3 4 5 6 7 8 9 10 11 11 12 13 14 15 16 17 18
Pin Name
AVSS RP VCO AVDD TEST1 TEST2 HFLY VS HSYNC SDA SCL DVDD N/C FBLK ROUT GOUT BOUT PB DVSS
Direction
I/O I/O Input Input Input Input Input I/O Input Output Output Output Output Output -
Digital/Analog
Supply Analog Analog Supply Digital Digital Digital Digital Digital Digital Digital Supply Digital Digital Digital Digital Digital Supply Analog Ground for VCO for VCO
Function
Analog Power Supply Remains at 0 (for test purposes only) Remains at 0 (for test purposes only) Horizontal Flyback Input Vertical Synchronization Input Horizontal Synchronization Input Serial Data of IC bus Serial Clock of IC bus Digital Power Supply Fast Blanking Output OSD Red Color Output OSD Green Color Output OSD Blue Color Output PictureBooSTTM Output Digital Ground
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General Description
Table 1: Pin Descriptions (Continued) N
19 20 21 22 23 24
STV9937
Pin Name
DVDD IVDD RIN GIN BIN IVSS
Direction
Input Input Input -
Digital/Analog
Supply Supply Analog Analog Analog Supply Digital Power Supply
Function
Power Supply for Video Input VGA Signal Input, Red Channel VGA Signal Input, Green Channel VGA Signal Input, Blue Channel Ground for Video Input
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STV9937
Register Addressing
2
Register Addressing
All OSD control registers are located in Window 0, Row 0. PictureBooSTTM control registers are located in Window 0, Row 1. All color-boxes data are located in Window 0, Row 2. Three formats are available: A, B and C, as described in the IC protocol (see Section 2.1: IC Protocol). All addresses (FAC and FWR bytes) are based on Formats A or B, and are written in hexadecimal format.
2.1
IC Protocol
The serial interface with the microcontroller is an IC bus with 2 wires: SCL and SDA.The OSD is a slave circuit with 2 modes: Write and Read. The slave address of the OSD is BAh in write mode and BBh in read mode.
2.1.1
Data to Write
In the OSD, the IC bus is used to write - read:

the control data the character codes and their respective color codes the color-boxes (8 color-boxes per window).
A color-box contains the character color, character background color and blink data. There are 8 color-boxes for each OSD window which are used to define the colors available for all the characters of the given OSD window. 3 bits are required to code the 8 color-boxes. These bits are the color code. For more information, refer to Section 4.5: Character Colors on page 22. Each character code is related to its own window, row and column. Consequently, the protocol of the IC transmission includes this information (window, row and column) to define the position of the character on the screen. These 3 pieces of information about the position are transmitted in 2 bytes. As each character on the screen has its own color code, the same protocol is used to write all the color codes and character codes. Only the attribute bit called `A' allows the character codes to be distinguished from the color codes corresponding to one position on the screen. The control data is also written with the same protocol using windows, rows and columns. Window 0 is reserved for control data and color codes.
2.1.2
Transmission Formats
There are 3 transmission formats to suit the amount of data to update. The transmission format is coded in the "window/row/column" bytes. Format A is suitable for updating small amounts of data which are allocated to different window, row and column addresses. Format B is recommended for updating data for the same window and the same row address, but with a different column address and when changing the Character/Color-box attribute (bit A), or when writing to a different IC control register. Format C is appropriate for updating large amounts of data from a full window or full screen. The window, row and column addresses are incremented automatically when this format is applied. Data is written to fill all the allocation memory of the windows.
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Register Addressing
The transmission formats are as follows: 1. Format A: S-FWR-FAC-D (R) FWR-FAC-D (R) FWR-FAC-D (R) FWR-FAC-D...Stop 2. Format B: S-FWR-FAC-D (R) FAC-D (R) FAC-D (R) FAC-D...Stop 3. Format C: S-FWR-FAC-D (R) D (R) D (R)D...Stop Where: S = Slave address = BAh FWR = Format, Window and Row address FAC = Format, Attribute and Column address
STV9937
D = CTRL Control data (8 bits), CB Color codes (3 bits) or RC Character codes (9 bits). In Format C, the order of automatic incrementation for data D is first the column value, then the row value, and then the window value.
Table 2: Various Bytes coded in the IC Transmission Byte FWR FAC D: Control Data (in window 0 only) D: Color Code and Character Code MSB D: Character Code LSBs 0 0 0 Bit 7
1 0
Bit 6
Bit 5 W[2:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R[3:0] C[4:0] CTRL[7:0] RC[8] 0 CB[2:0]
F
A
RC[7:0]
2.1.3
Format, Window and Row Address (FWR)
Bit 7 indicates the `Window & Row' byte when set to 1. W[2:0]: Window Number 000: Control Data and Color Codes 001: Window 1 010: Window 2 011: Window 3 100: Window 4 R[3:0]: Row Numbers from 0 to 15. Each window has a maximum number of 16 rows.
2.1.4
Format, Attribute and Column Address (FAC)
Bit 7 indicates the `Attribute & Column' byte when set to 0. F: Format 0: Format A or B 1: Format C A: Transmission of character code or color code 0: Character Code 1: Color Code and Character Code MSB When reading or writing control data and/or character codes, bit A must be set to 0. For color code and character code MSB, bit A must be set to 1.
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STV9937
C[4:0]: Column Number There are 32 possible columns. 00000: 1 column 11111: 32 columns
Register Addressing
2.1.5
Control Data, Color Codes or Character Codes
Color codes are stored on 3 bits. Control data is stored on 8 bits and Character codes are stored on 9 bits.
2.1.6
Configuration of Transmission Formats
Table 3: Configuration of Transmission Formats Byte
Windows & Rows
Format
A, B or C A or B C A, B or C A or B C
Bit 7
1 0 0 1 0 0
Bit 6
Bit 5
W[2:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FWR FAC FAC FWR FAC FAC
R[3:0] C[4:0] C[4:0] R[3:0] C[4:0] C[4:0]
Address bytes for Characters Codes
Column (A and B) Column (C) Windows & Rows
0 1
0 0 W[2:0]
Address bytes Column (A and B) for Color Codes Column (C)
0 1
1 1
All formats must start with the S, FWR and FAC bytes.
2.2
Format Changing
To change from Format A to Format B
S-FWR[0]- FAC[0]-D[0] (R) FWR[1]- FAC[1]- D[1] (R) FWR[2]- FAC[2]- D[2] (R) FAC[3]- D[3] (R) FAC[4]D[4] (R) FAC[5]- D[5]... The F bit from the FAC byte is always 0 in this case.
To change from Format A to Format C
S - FWR[0]- FAC[0]- D[0] (R) FWR[1]- FAC[1]- D[1] (R) FWR[2]- FAC[2]- D[2] (R) D[3] (R) D[4] (R) D[5]... The "F" bit from the FAC byte is as follows: F[0] = F[1] = "0" F[2] = "1"
To change from Format B to Format A
S - FWR[0]- FAC[0]-D[0](R) FAC[1]- D[1] (R) FAC[2]-D[2] (R) FWR[3]- FAC[3]- D[3] (R) FWR[4]- FAC[4]D[4]... The F bit from the FAC byte is always 0 in this case.
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Register Addressing To change from Format B to Format C
S - FWR[0]- FAC[0]- D[0] (R) FAC[1]- D[1] (R) FAC[2]- D[2] (R) D[3] (R) D[4]... The "F" bit from the FAC byte is as follows: F[0] = F[1] = "0" and F[2] = "1" It is not possible to change from Format C back to Format A or B.
Figure 5: Format Changing Sequences
STV9937
Start start
Format A
Format C
Format B
2.3
Read Mode
The transmission format is shown as below: Start - S(w) - FWR- FAC - Stop - Start - S(r) - D (R) D (R) D (R) D...Stop Where: S(w) = Slave address in write mode = BAh = 10111010, S(r) = Slave address in read mode = BBh = 10111011. Registers and data in RAM are readable. This mode is useful when developing OSD applications.
2.4
Addressing Map
Table 4: Window Addressing Map Window Row
Row 0 Row 1 Row 2 Rows 0 to n (n = 15 max.)
Column
Columns 0 to 31 Columns 0 to 31 Columns 0 to 31 Columns 0 to m (m = 31 max.)
Data
Control Data (8 bits) PictureBooSTTM Data Color-boxes (8 bits) Characters Coding (12 bits)
Window 0 Window 0 Window 0 Windows 1, 2, 3 and 4
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STV9937
Window Specifications
3
Window Specifications
Four different independent windows with separate character displays can be simultaneously displayed on screen. It is possible to have overlapping windows with an automatic control of display priorities: downscale priorities from Window 4 to Window 1. Window 1 is well-adapted for the OSD general menu. The 4 windows, each with its own character display, can be positioned anywhere on the screen. The following characteristics are defined for each window:

Enable Display Position Size, adjustable with memory allocation Background Color Bordering or Shadowing effects with programmable color, height and width.
Figure 6: Example of Window Displays
Screen Axis Origin VD HD Window 2
Window 1
Window 3 Window 4
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Window Specifications
STV9937
3.1
Enable Display
The Enable Display command for each window is selected by bits ENW1, ENW2, ENW3 and ENW4. If the ENWi bit is set to 1, the corresponding window is displayed.
Table 5: Enable Display
FWR
80h
FAC
07h
Default
0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ENW4
Bit 2
ENW3
Bit 1
ENW2
Bit 0
ENW1
3.2
Origin Positions for the 4 Windows
The 4 windows are arranged in a frame whose origin coordinates are the horizontal delay (HD) and the vertical delay (VD) located at the upper left-hand corner of the monitor screen. When the HD and VD values are changed, the 4 windows within the frame position are automatically shifted by the same value. The origin (HD, VD) can be programmed anywhere on the screen. Adjusting the origin position is used to globally reposition the OSD windows. The advantages of this system are easier programming, the possibility to adapt the position of all windows at a single time without changing the relative position of each window and the possibility for the user to program all 4 window positions.
3.2.1
General Horizontal Delay (HD)
Table 6: Origin of Windows on Horizontal Axis: Horizontal Delay
FWR
80h
FAC
04h
Default
0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
HD[6:0]
Bit 2
Bit 1
Bit 0
The general horizontal delay defines the horizontal position of the origin coordinate for all four OSD windows. The horizontal delay is selected by bits HD[6:0]. General Horizontal Offset = 50 pixels General Horizontal Delay = HD[6:0] x 6 pixels + General Offset (in pixels) The default value of the horizontal delay is 0h (left-hand side of the monitor screen).
3.2.2
General Vertical Delay (VD)
Table 7: Origin of Windows on Vertical Axis: Vertical Delay
FWR
80h
FAC
05h
Default
0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VD[7:0]
The general vertical delay defines the vertical position of the origin coordinate for all four OSD windows. The vertical delay is selected by bits VD[7:0]. A general vertical offset of 2 scan lines is also applied. The range of the vertical delay is from 2 to 1022 scan lines, in steps of 4 scan lines each. General Vertical Delay = VD[7:0] x 4 + 2 (in scan lines) The default value of the vertical delay is 0h (top of screen).
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STV9937
Window Specifications
3.3
Window Positions in the Frame
All values are referenced to the origin coordinates (HD, VD). For more information, refer to Figure 6 on page 13.
3.3.1
Window Horizontal Delay
The window horizontal delay defines the horizontal start position for each separate OSD window. This value is selected by bits HDW1[6:0], HDW2[6:0], HDW3[6:0] and HDW4[6:0], respectively.
Table 8: Window Horizontal Delay
FWR
80h
FAC
0Ch, 11h, 16h, 1Bh
Default
0h, 20h, 0h, 10h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
HDWi[6:0]
Bit 2
Bit 1
Bit 0
The range of the window horizontal delay is from 0 to 1524 pixels, in steps of 12 pixels each. Window Horizontal Delay = HDWi[6:0] x 12 pixels The total horizontal delay of a window is: General Horizontal Delay + HDWi[6:0] x 12 pixels; or, HD[6:0] x 6 pixels + HDWi[6:0] x 12 pixels + (50 pixels). The default values for the window horizontal delay for each of the four OSD windows is given in Table 8.
3.3.2
Window Vertical Delay
The window vertical delay defines the vertical start position for each separate OSD window. This value is selected by bits VDW1[5:0], VDW2[5:0], VDW3[5:0] and VDW4[5:0], respectively.
Table 9: Window Vertical Delay
FWR
80h
FAC
0Dh, 12h, 17h, 1Ch
Default
0h, 0h, Ch, Ch
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VDWi[5:0]
The range of the window vertical delay is from 0 to 63 rows of characters, in steps of 1 character row each. It is important to note that the height of each character row is defined by the row height parameter. For more information, refer to Section 4.4: Space Lines on page 21. Window Vertical Delay = VDWi[5:0] x Row_Height The total vertical delay of a window is: General Vertical Delay + VDWi[5:0] x Row_Height (in scan lines); or, (VD[7:0] x 4 + 2) + VDWi[5:0] x Row_Height (in scan lines). The default values for the window vertical delay for each of the four OSD windows is given in Table 9.
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Window Specifications
STV9937
3.4
3.4.1
Window Size: Number of Character Rows and Character Columns
Window Horizontal Size
The window horizontal size defines the number of characters displayed for character row for each separate OSD window. This value is selected by bits HSW1[4:0], HSW2[4:0], HSW3[4:0] and HSW4[4:0], respectively.
Table 10: Window Horizontal Size
FWR
80h
FAC
0Eh, 13h, 18h, 1Dh
Default
19h, 9h, Fh, Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
HSWi[4:0]
Bit 1
Bit 0
The range of the window horizontal size is from 1 to 32 characters, in steps of 1 character each. Each character is 12 pixels long. There is an offset of 1 character. Window Horizontal Size = HSWi[4:0] +1 characters The default values for the window horizontal size for each of the four OSD windows is given in Table 10.
3.4.2
Window Vertical Size
The window vertical size defines the number of character rows displayed for each separate OSD window. This value is selected by bits VSW1[3:0], VSW2[3:0], VSW3[3:0] and VSW4[3:0], respectively.
Table 11: Window Vertical Size
FWR
80h
FAC
0Fh, 14h, 19h, 1Eh
Default
Bh, 4h, 7h, 7h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VSWi[3:0]
The range of the window vertical size is from 1 to 16 character rows, in steps of 1 character row each. It is important to note that the height of each character row is defined by the row height parameter. For more information, refer to Section 4.4: Space Lines on page 21. There is an offset of 1 character row. Window Vertical Size = (VSWi[3:0] + 1) x Row_Height (in scan lines) Row_Height = Character_Height + 2 x Space_Lines The default values for the window vertical size for each of the four OSD windows is given in Table 11. Table 12 shows an example of the origin and size of windows based on the example shown in Figure 8,
Table 12: Example of Origin and Size of Windows Window i Window 1 Window 2 HD
0 5
VD
2 0
HSWi
7 4
VSWi
4 5
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STV9937
Table 12: Example of Origin and Size of Windows Window i Window 3 Window 4 HD
6 3
Window Specifications
VD
4 7
HSWi
6 4
VSWi
3 4
3.5
Window Background Color
The window background color for each separate OSD window is coded over 4 bits as shown in Table 13. The first bit (Ti) specifies whether the background is transparent or if a color is displayed. If the background is transparent (Ti = 1), the active video is displayed as background. If a color is displayed (Ti = 0), the background color for each separate OSD window is coded over the last three bits (RWi, GWi and BWi, respectively). Windows are displayed with a white background by default (7h).
Table 13: Background Color of Each Window
FWR
80h
FAC
10h, 15h 1Ah, 1Fh
Default
7h, 7h, 7h, 7h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Ti
Bit 2
RWi
Bit 1
GWi
Bit 0
BWi
3.6
3.6.1
Window Bordering and Shadowing Effects
Enable Bordering or Shadowing Effects
Bordering or shadowing effects are enabled for each separate OSD window by bits ENBS1, ENBS2, ENBS3 and ENBS4, respectively.
3.6.2
Bordering or Shadowing Selection
Either the bordering or the shadowing effect is selected for each separate OSD window by bits BSW1, BSW2, BSW3 and BSW4, respectively.
Table 14: Bordering and Shadowing Parameter Selection Bit
ENBSi BSWi
Description
0: No Bordering, No Shadowing (Default Value) 1: Bordering or Shadowing is selected. 0: Bordering is selected (Default Value) 1: Shadowing is selected.
Table 15: Enable Bordering or Shadowing Effects FWR
80h 80h
FAC
07h 10h, 15h 1Ah, 1Fh
Default
0h 0h, 0h, 0h, 0h
Bit 7
ENBS4
Bit 6
ENBS3
Bit 5
ENBS2
Bit 4
ENBS1 BSWi
Bit 3
Bit 2
Bit 1
Bit 0
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Window Specifications 3.6.3 Border or Shadow Color
STV9937
The border or shadow color is separately programmable for each separate OSD window. This value is selected by bits WSRi, WSGi and WSBi for each of the four OSD windows. The value for each color is shown in Table 17.
Table 16: Border or Shadow Color FWR
80h
FAC
10h, 15h 1Ah, 1Fh
Default
0h, 0h, 0h, 0h
Bit 7
WSRI
Bit 6
WSGI
Bit 5
WSBI
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 17: Bordering and Shadowing Color Selection (WSRGBi) Value
000 001 010 011
Color
Black (Default) Blue Green Cyan
Value
100 101 110 111
Color
Red Magenta Yellow White
3.6.4
Bordering or Shadowing Size
The size of the bordering or shadowing width is separately programmable for each separate OSD window. This value is selected by bits BSWWi[2:0] for each of the four OSD windows. The width size is from 0 to 14 pixels, in steps of 2 pixels each. Width Size = BSWWi[2:0] x 2 pixels The size of the bordering or shadowing height is selected by bits BSHWi[3:0] for each of the four windows. The height size is from 0 to 30 lines, in steps of 2 scan lines each. Height Size = BSHWi[3:0] x 2 scan lines.
Table 18: Bordering or Shadowing Size
FWR
80h 80h
FAC
0Eh, 13h 18h, 1Dh 0Fh, 14h 19h, 1Eh
Default
0h, 0h, 0h, 0h 0h, 0h, 0h, 0h
Bit 7
Bit 6
BSWWi[2:0]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BSHWi[3:0]
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STV9937
Window Specifications
Figure 7: Illustration of Window Bordering and Shadowing Effects M pixels Window Shadowing N scan lines
N scan lines Window Bordering M pixels
3.7
Window Display Priority Management
The OSD windows are displayed with the following priority: Window 4 (top), 3, 2 and 1 (bottom). This order of priority is shown the example given in Figure 8.
Figure 8: Example of Window Displays
Screen Axis Origin VD HD Window 2
Window 1
Window 3 Window 4
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Character Specifications
STV9937
4
4.1
Character Specifications
General Description
There are:

496 monochrome characters and 16 multi-color characters in ROM 32 to 127 characters per line character height varies between 18 and 127 scan lines 0 to 62 scan space lines between character rows, with the same number of lines above and below the rows of characters. blinking effect for each character shadowing effect for characters in each window background and foreground character colors: for each character, among a Color-shop of 8 Color-boxes per window. There is a Color-shop for each window. The Color-boxes define the background colors and the foreground character colors and blinking effect.
With the possibility to select:

4.2
Horizontal Resolution
Table 19: Horizontal Resolution
FWR
80h
FAC
01h
Default
20h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
HR[6:0]
Bit 2
Bit 1
Bit 0
The horizontal resolution defines the number of pixels per line expressed in characters unit. This value is selected by bits HR[6:0]. The range of the horizontal resolution is from 32 to 127 characters, in steps of one character each. The default value is 32 characters per line (20h). If bits HR[6:0] are programmed with a value less than 32, the horizontal resolution will be 32 characters per line (minimum value). HR[6:0] = Number of characters per line It is important that the maximum pixel frequency must be respected (CLK2= 120 MHz maximum). As each character is 12 pixels long, the number of pixels per line varies from 384 to 1524. For more information, refer to Section 6: Pixel Clock Generator on page 29.
4.3
Character Height
Table 20: Vertical Character Height
FWR
80h
FAC
02h
Default
12h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CH[6:0]
Bit 2
Bit 1
Bit 0
The vertical height defines the number of scan lines used to display the characters. This value is selected by bits CH[6:0].
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STV9937
The range of the vertical height is from 18 to 127 lines. CH[6:0] = Number of scan lines used to display the characters
Character Specifications
The characters stored in ROM are coded on 18 lines. If bits CH[6:0] are programmed with a value less than 18, the characters will be automatically displayed with a height of 18 scan lines (minimum value). When a multiple of 18 scan lines are displayed, all ROM lines are repeated N number of times, with N in the range of 1 to 7, so as not to exceed the display of 127 scan lines. For example, if CH[6:0] = 36, each ROM line is repeated twice. If the number of scan lines displayed is not a multiple of 18, certain ROM lines are repeated more often than others, as shown in Table 21. For example, if CH[6:0] = 40, each ROM line is repeated twice and ROM lines 3, 7, 10 and 14 are repeated three times. Table 21 shows which ROM lines, from 0 to 17, are repeated depending on the CH[6:0] value.
Table 21: Repeated ROM Lines1 CH Value
18, 36, 54, 72, 90, 108, 126 19, 37, 55, 73, 91, 109, 127 20, 38, 56, 74, 92 ,110, 21, 39, 57, 75, 93, 111 22, 40, 58, 76, 94, 112 23, 41, 59, 77, 95, 113 24, 42, 60, 78, 96, 114 25, 43, 61, 79, 97, 115 26, 44, 62, 80, 98, 116 27, 45, 63, 81, 99, 117 28, 46 ,64, 82, 100, 118 29, 47, 65, 83, 101, 119 30, 48, 66, 84, 102, 120 31, 49, 67, 85, 103, 121 32, 50, 68, 86, 104, 122 33, 51, 69, 87, 105, 123 34, 52, 70, 88, 106, 124 35, 53, 71, 89, 107, 125
A
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
1. `R' = Repeated ROM lines `A' = Number of additional repeated lines
4.4
Space Lines
The space lines define the number of scan lines above and below each character row. This value is selected by bits RSPA[4:0]. The total row height is defined as follows: Row_Height = Character_Height + 2 x Space_Lines (see Figure 9)
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Character Specifications
STV9937
The range of spacing lines is from 0 to 31 scan lines, in steps of one scan line each. The default value is 0 scan lines. The space lines are displayed in the color of the associated character background.
Table 22: Row Height (Space Lines) FWR
80h
FAC
03h
Default
0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RSPA[4:0]
Bit 1
Bit 0
Figure 9: Row Height Definition
RSPA[4:0] Space Lines
Total Row Height
AB
CH[6:0] Character Height
RSPA[4:0] Space Lines
4.5
Character Colors
The colors for the characters, character background and blinking effect is separately programmable for each OSD window. The color values are stored in a color-shop of 8 color-boxes for each window. There are 4 color-shops, 1 per window, offering the user 32 possibilities of character coloring. As the color-boxes are in RAM, the user must write to the color-box prior to using it. Color-box data is stored in Window 0, Row 2. For more information, refer to Section 2.4: Addressing Map on page 12.
Table 23: color-box
FWR
82h
FAC
00h to 1Fh
Default
Bit 7
BC
Bit 6
BR
Bit 5
BG
Bit 4
BB
Bit 3
BLINK
Bit 2
FR
Bit 1
FG
Bit 0
FB
4.5.1
Character Background Color
A character background color can be separately programmed for each of the color-boxes. This value is selected by bits BC, BR, BG and BB. For more information concerning the window background color, refer to Section 3.5: Window Background Color. Bit BC is used to define if a specific character background color will be displayed or if the character background color is the color of the window background.
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STV9937
Character Specifications
If a specific character background color is selected for a color-box, the character background color is selected by bits BR, BG and BB.
Table 24: Character Background Color Color
Black Blue Green Cyan Red Magenta Yellow White Window Background Color 1
BC
1 1 1 1 1 1 1 1 0
BR
0 0 0 0 1 1 1 1
BG
0 0 1 1 0 0 1 1
BB
0 1 0 1 0 1 0 1
1. See Table 25
.
Table 25: Background Color Priority BC
1 0 0
TI
X 0 1
Background Color
Character Background Color (BR, BG and BB) Window Background Color (RGBWi) Transparent Background (Video active)
4.5.2
Character Color
A character color can be separately programmed for each of the color-boxes. This value is selected by bits FR, FG and FB.
Table 26: Character Colors Color
Black Blue Green Cyan Red Magenta Yellow White
FR
0 0 0 0 1 1 1 1
FG
0 0 1 1 0 0 1 1
FB
0 1 0 1 0 1 0 1
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Character Specifications 4.5.3 Character Blinking Effect
STV9937
A character blinking effect can be separately programmed for each of the color-boxes. This value is selected by the BLINK bit. When this bit is set to 1, the blinking effect is enabled and the characters blink.
4.6
Character Shadowing
A character shadowing effect can be separately programmed for each of the color-boxes. This value is selected by bits CSHA[3:0], respectively. The shadowing color is black. When this bit is set to 1, the characters of the corresponding OSD window are displayed with a shadowing effect, as shown in Figure 10. The default value is 0 (no shadowing effect).
Figure 10: Character Shadowing
Table 27: Character Shadowing FWR
80h
FAC
08h
Default
0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSHA[3:0]
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STV9937
Character Specifications
4.7
Character Font
Figure 11 shows the available character font stored in ROM.
Figure 11: Character Fonts
0 1 2 3 4 5 6 7 8 9ABCDE F 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
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RAM Specification
STV9937
5
5.1
RAM Specification
Character Coding
Each character to display is coded with 12 bits in the RAM with the following addressing method:

Character Code: Bits RC[8:0] are used to address the ROM Code Color Code: Bits CB[2:0] are used to select 1 of the 8 color-boxes in the color shop of the corresponding OSD window.
Table 28: Character Coding
FWR
FAC
Bit 11
Bit 10
CB[2:0]
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
RC[8:0]
Bit 3
Bit 2
Bit 1
Bit 0
See Table 3
5.2
Window Memory Allocation
The 4 OSD windows can be distributed differently. But the displayable windows will always contain a total of 20 blocks (1 block consists of 32 characters).
Figure 12: Window Memory Space
1 Block
Window 0 Color-boxes
10 Blocks
Window 1
4 Blocks
Window 2
Displayable Windows
3 Blocks
Window 3 Window 4
3 Blocks
5.3
Memory Size Allocation
The total number of characters or spaces is up to 640 with a maximum window size of 16 rows of 32 characters. The character codes of each window are allocated to a specific memory space. This memory space is programmable for each window. The window size must be less than or equal to its memory allocation. Any window size can be modified within its specific memory space, the other windows are not affected by this operation.
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STV9937
RAM Specification
The user must reserve a memory space for the largest window. According to the example shown in Figure 6, the total number of characters/spaces are:
Table 29: Window Sizes Window Window 1 Window 2 Window 3 Window 4 Total Size
28 20 18 16 82
For example, to change the size of Window 3 from 3 rows of 6 characters to 5 rows of 4 characters, the resulting size is 20 characters. The number of rows increases and the number of characters per row decreases. The required memory is at least 20 characters. Note: A space is considered as being a character. The memory allocation is made by blocks of 32 characters. The maximum size of a window is 16 rows of 32 characters, or 512 characters. This corresponds to 16 blocks of 32 characters. 1 block is reserved for the color-boxes (see Chapter 4: Character Specifications on page 20), leaving 20 blocks of 32 characters for character codes (640 characters maximum). The RAM allocation for each window is coded in bits ALWi[3:0]. Window 4 memory allocation uses the remaining memory space.
Table 30: Window RAM Allocation FWR
80h 80h
FAC
09h 0Ah
Default
39h 2h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALW2[3:0]
ALW1[3:0] ALW3[3:0]
The number of memory blocks allocated for window "i" is (ALWi +1), the range of allocation is 1 to 16 blocks of 32 characters. The total number of blocks is 20. Note: If the user changes only 1 window allocation, the RAM addresses of the following windows change. Consequently we advise you to write the allocation when the windows are not displayed to avoid false images.
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RAM Specification
The default window RAM allocations are listed in Table 31.
Table 31: Window RAM Default Values ALWi
ALW1 ALW2 ALW3
STV9937
Default
9h 3h 2h
Description
320 Characters (10 blocks) 128 Characters (4 blocks) 96 Characters (3 blocks)
Window 1: 10 blocks of 32 words = 320 characters (ALW1 = 9). Window 2: 4 blocks of 32 words = 128 characters (ALW2 = 3). Window 3: 3 blocks of 32 words = 96 characters (ALW3 = 2). Window 4: the remaining RAM (3 blocks = 96 characters).
5.4
Window Reset
All the RAM data from one of the four OSD windows can be reset by writing to bits RESETW[3:0]. When the RESETW bit is set to 1, all the RAM data in the allocation memory space of the corresponding OSD window is reset. These bits are automatically cleared when the RAM allocation reset is finished.
Table 32: RAM Allocation Enable and Reset
FWR
80h
FAC
0Bh
Default
0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETW[3:0]
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STV9937
Pixel Clock Generator
6
Pixel Clock Generator
The Pixel Clock Generator is used to synchronize the display clock with the horizontal synchronisation (Hsync) signal. This generator is based on a PLL function used to perform correct jitter. The pixel frequency is defined with the horizontal line frequency and the horizontal resolution. Pixel Frequency (FPIXEL2) = 12 x HR[6:0] x fHLINE The VCO[1:0] value is used to select the appropriate curve partition of the VCO.
Table 33: VCO Curve Partition VCO Value (Binary)
00 01 10 11
VCO Curve Partition 7.68 MHz < FPIXEL2 < 15 MHz (Default Value)
15 MHz < FPIXEL2 < 30 MHz 30 MHz < FPIXEL2 < 60 MHz 60 MHz < FPIXEL2 < 120 MHz
Table 34: VCO Range FWR
80h
FAC
00h
Default
0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO[1:0]
The PLL generates:

a pixel clock for the OSD from 7.68 MHz to 120 MHz: FPIXEL2 a pixel clock for the PictureBooSTTM (PB) from 30 to 60 MHz: FPIXEL1.
The PictureBooSTTM pixel clock provides the resolution of the PB pixel.It is locked on the HSYNC signal and the referenced edge is programmed using the HSP bit. When the monitor resolution is changing, the micro controller changes the OSD horizontal resolution to adapt the width of the OSD window. In this case, the frequency of the PB clock is changing also. So the width and the position and the resolution of the PB window is changing.
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Picture BooSTTM
STV9937
7
Picture BooSTTM
Picture BooSTTM allows images to be boosted either within a window, a screen area or over the entire screen. To perform this function, the STV9212 preamplifier is required as well as the Picture BooSTTM software which sends the window or screen area coordinates (X1, X2,Y1,Y2) to the RGB video channels. The Picture BooSTTM system embedded in the STV9937 includes:

The RGB Comparator The Coordinate Decoder The Control and Data registers
The STV9937 computes the data received on the RGB channel and generates a BooST signal which is then sent to the STV9212. The coordinates can be received through the IC bus by the MCU as well. The STV9937 also includes three 8 bits register used to store data received by RGB.
7.1
Video RGB Input Stage
The input stage is a triple analog-digital buffer for the video RGB inputs.

The input voltage range is 0 to 0.7 V The inputs have to be supplied through a serial capacitor (100nF) The input RGB must be set to `0' during the horizontal sync.
The input stage includes a clamping function using the Hsync signal to fix the DC level of inputs.
Figure 13: Hsync Clamping Function
THTCL
100nF HSYNC AND
ENCL
CLP
The input stage is configured by three control bits; THCTL, CLP and ENCL as shown in Figure 37.
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STV9937
Picture BooSTTM
7.2
PictureBooSTTM RGB Decoder
The STV9937 can receive the coordinates of the area to BooST through the RGB channel or through IC bus. The Picture BooSTTM area coordinates are coded as follows:
Table 35: PictureBooSTTM Window Coordinates Bits
X1[12:0] X2[12:0] Y1[10:0] Y2[10:0]
Description
Left coordinate of the window, in CLK1 pixels (FPIXEL1) Right coordinate of the window, in CLK1 pixels Top coordinate of the window, in lines Bottom coordinate of the window, in lines
7.2.1
Data Sent Using IC
Before sending data to the corresponding registers, the PBVM bit must be set to 1. Then the coordinates can be sent to the corresponding address, see Table 36:

Row 1, Col 3 to 6 for X1, X2 coordinates Row 1, Col 7 to 10 for the Y1, Y2 coordinates.
7.2.2
Data Sent Using the RGB Channel
The Picture BooSTTM Software sends coordinate data through the RGB channel:

The Red channel contains the X1, X2 and Y1, Y2 coordinates information The Green Channel contains a specific activation code The Blue Channel contains the clock signal. Row 1, Col 3 to 6 for X1, X2 coordinates Row 1, Col 7 to 10 for the Y1, Y2 coordinates.
The Decoder stores the coordinates values to the corresponding address:

X1 and X2 are referred to the HSYNC signal, the resolution is FPIXEL1 (from 30 Mhz to 60 Mhz)
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Picture BooSTTM
STV9937
In the same way, 3 other 8 bits of register data(D3A, D3B and D3C)can be sent via the video RGB and detected by the STV9937. These three registers can be read by the IC bus at Row1, Col 11 to 13. This specific data cannot be written by IC.
Figure 14: PictureBoostTM area Coordinates
HSYNC
X1
X2
VSYNC
Screen
Y2
Y1
(X1, Y1)
BOOSTED AREA
Window 3 (X , Y ) 2 2
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STV9937
Picture BooSTTM
7.3
Control Registers Description
Table 36: Control Registers PB: Window 0, W[2:0] = "000", row = 1 R[3:0] ="0001"
Address Bit 7 Row
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 6
THCTL
Bit 5
CLP
Bit 4
ENCL
Bit 3
HFLYP Reserved
Bit 2
OSDREF Reserved
Bit 1
Reserved PBVM
Bit 0
ENPB PBON
Col.
0 1 2 3 4 5 6 7 8 9 A B C D E F 1x 1F HMUX 0 0 0 Y2[7:0] D3A[7:0] D3B[7:0] D3C[7:0] Reserved Reserved Reserved 0 0 0 0 Y1[7:0] Y2[10:8] X2[7:0] Y1[10:8] X1[7:0] X2[12:8] OFFSETLIN[1:0]
OFFSETPIX[5:0] X1[12:8]
Table 37: PictureBooSTTM Configuration Bit
THCTL
Description
The THCTL bit selects the thresholds of the input voltage (low or high) 0: Low thresholds selected 1: High thresholds selected (Default value) The CLP bit selects the polarity of the Hsync signal for the clamp 0: Clamp when Hsync = 1 (Default value) 1: Clamp when Hsync = 0 The ENCL bit enables the clamping function for the RGB input stage 0: Clamping disabled 1: Clamping enabled (Default value)
CLP
ENCL
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Picture BooSTTM
Table 37: PictureBooSTTM Configuration Bit
HFLYP
STV9937
Description
The HFLYP bit configures the polarity of the HFLY signal 0: Falling edge active (default value) 1: Rising edge active The OSDREF selects the signal taken as reference 0: HFLY is the reference (default value) 1: HSYNC is the reference The ENPB bit selects Picture BooSTTM decoding 0: The RGB video inputs are not decoded, there is no possibility of displaying the PB. The user can write X1/X2 Y1/Y2 coordinates in the registers, but the On/Off bit is inactive (default value) 1: PB decoding is active and the PB display can be made active with the PBON bit The PBON bit selects Picture BooSTTM display 0: PB is not displayed (default value) 1: PB is displayed on the screen with the coordinates written in the X/Y registers The PBVM bit selects the Picture BooSTTM interface 0: Interface via RGB (default value) 1: Interface via IC
OSDREF
ENPB
PBON
PBVM
7.4
Line and Pixel Offsets
Due to the intrinsic delay on the RGB channel during the RGB decoding, 2 offsets can be applied for fine tuning as shown in below:
Bits
OFFSETLIN[1:0] OFFSETPIX[5:0]
Description
The line offset in SIGNED radix is coded on 2 bits from -2 to +1. Default value is 0. The pixel offset in SIGNED radix is coded on 6 bits from -32 to +31. Default value is 0.
Note:It is recommended to adjust the pixel offset each time the monitor resolution changes.
7.5
PLL Synchronised
The STV9937 PLL can either be synchronized on the HFLY or HSYNC signals.
WARNING:Once synchronized on HFLY, the Picture BooSTTM feature cannot be guaranteed.
Bit
HMUX
Description
0: HSYNC is the synchronization signal 1: HFLY is the synchronization signal
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STV9937
General OSD Programming
8
8.1
General OSD Programming
Enable OSD
The OSD window displays are enabled by the ENOSD bit. ENOSD = 1: OSD window displays are active. ENOSD = 0: OSD window displays are inactive. Pin FBLK = 0 and pins ROUT, GOUT and BOUT pins = 0 (bit RGBPOL is 0). The default value is 0.
Table 38: Enable OSD FWR
80h
FAC
00h
Bit 7
Bit 6
Bit 5
Bit 4
ENOSD
Bit 3
Bit 2
Bit 1
Bit 0
8.2
Fade-in and Fade-out Effect
The Fade-in and Fade-out effect is used to progressively increase/decrease the OSD window to/ from its full size. This effect is enabled by the FADE bit. FADE = 1: Fade effect is active FADE = 0: Fade effect is inactive (default value)
Table 39: Fade
FWR
80h
FAC
00h
Bit 7
Bit 6
Bit 5
FADE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8.3
Full Screen Display
The STV9937 allows a full screen display with a selectable color programmable by the FBK bit as follows: FBK = 1: The video area is replaced by the color coded in bits FSR, FSG and FSB (full screen color values). Pin FBLK is always 1. FBK = 0: Normal video mode whether or not the OSD menu is displayed. The default value of bit FBK is 0.
Table 40: Full Screen Registers
FWR
80h 80h
FAC
01h 03h
Default
0h 0h
Bit 7
FBK FSR
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FSG
FSB
Table 41: Full Screen Colors Color
Black (Default Value) Blue Green
FSR
0 0 0
FSG
0 0 1
FSB
0 1 0
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General OSD Programming
Table 41: Full Screen Colors (Continued) Color
Cyan Red Magenta Yellow White
STV9937
FSR
0 1 1 1 1
FSG
1 0 0 1 1
FSB
1 0 1 0 1
8.4
Signal Polarity and Triggering
Table 42: Signal Polarity
FWR
80
FAC
00
Default
Bit 7
FBKPOL
Bit 6
RGBPOL
Bit 5
Bit 4
Bit 3
VSP
Bit 2
HSP
Bit 1
Bit 0
Vertical Sync Triggering (VS input)
The active edge of the VS pin used for vertical synchronization is selected by bit VSP. VSP = 0: The falling edge is active. (Default Value) VSP = 1: The rising edge is active.
Horizontal Sync Triggering (HSYNC input)
The active edge of the HSYNC pin used for horizontal synchronization is selected by bit HSP. HSP = 0: The falling edge is active. (Default Value) HSP = 1: The rising edge is active.
RGB Output Polarity (ROUT, GOUT and BOUT outputs)
The output polarity of pins ROUT, GOUT and BOUT is selected by bit RGBPOL. RGBPOL = 0: RGB active at 1 (Default Value) RGBPOL = 1: RGB active at 0
Table 43: RGB Output Control
ENOSD Bit 1 1 0 0 RGBPOL Bit 0 1 0 1
RGB Outputs
Active at 1 Active at 0 000 111
Display
OSD OSD Video Video
36/49
STV9937 Fast Blanking Output Polarity (FBLK output)
General OSD Programming
The output polarity of the FBLK pin is selected by bit FBLKPOL. The default value is 0.
Table 44: Fast Blanking Output Polarity Selection FBLKPOL
0 1
Description
When OSD display, FBLK = 1 When active video, FBLK = 0 When OSD display, FBLK = 0 When active video, FBLK = 1
Table 45: FBLK Output Control
ENOSD Bit 1 1 1 1 1 1 0 0 FBLKPOL Bit 0 0 0 1 1 1 0 1
FBK Bit
0 0 1 0 0 1 x x
FBLK Output
0 1 1 0 1 0 0 1
Display
Video OSD OSD OSD Video OSD Video Video Default Value Full Screen FBLK Inverted Full Screen No OSD No OSD
8.5
Reset
Power On Reset
The digital core and the PLL are asynchronously reset at Power On.
Soft Reset
A soft reset is enabled by the RST bit. RST = 1: The digital core is reset. All control registers including PictureBooSTTM but with the exception of PLL registers, are reset at the same value as at power on reset. It is not necessary to write RST = 0 to stop the reset. This bit is automatically cleared.
PLL Register Reset
The Pixel Clock Generator (VCO[1:0]) and Horizontal Resolution (HR[6:0]) bits are reset by the RST_PLL bit. RST_PLL = 1: HR[6:0] and VCO[1:0] are reset to the same value as the power-on reset. It is not necessary to write RST_PLL = 0 to stop the reset. This bit is automatically cleared.
Table 46: Reset FWR
80h
FAC
06h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RST_PLL
Bit 0
RST
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Registers
STV9937
9
9.1
Registers
Register Specification
Control registers are located at address in Window 0, Row 0 and Row 1. Color-boxes are located at addresses in Window 0, Row 2. See Section 4.5 on page 22. Character codes are located at addresses in Windows 1 to 4, as described in Section 5.1 on page 26.
Table 47: Non-Displayable Window Register Mapping Register
OSD Control Registers PictureBooSTTM Control Registers Color-box Registers
Window
0 0 0
Row
0 1 2
FWR Code
80h 81h 82h
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STV9937
Registers
Table 48: Control Registers: Window 0, Row = 0 FWR
80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h
FAC
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Col
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Default
0h 20h 12h 0h 0h 0h 0h 0h 0h 39h 2h 0h 0h 0h 19h Bh 7h 20h 0h 9h 4h 7h 0h Ch Fh 7h 7h 10h Ch Fh 7h 7h
Bit 7
Bit 6
Bit 5
FADE = 0
Bit 4
ENOSD = 0
Bit 3
VSP = 0
Bit 2
HSP = 0
Bit 1
Bit 0
FBKPOL = RGBPOL 0 =0 FBK = 0
VCO[1:0] = 00
HR[6:0] :Horizontal Resolution = 32 characters CH[6:0] = Character Height = 18
full screen RGB = FS RGB = 000
RSPA[4:0] = Row Spacing = 0
HD[6:0] = Horizontal Delay Reference = 0 (50 pixels) VD[7:0] = Vertical Delay Reference = 0 (2 lines) RST_PLL =0 ENBS4/3/2/1 = 0000 ENW4/3/2/1 = 0000 CSHA[3:0] = 0 ALW2[3:0] = 3 (4 blocks = 128 characters) ALW1[3:0] = 9 (10 blocks = 320 characters) ALW3[3:0] = 2 (3 blocks, 96 characters) RESETW[3:0] = 0000 HDW1[6:0] = 0 VDW1[5:0] = 0 BSWW1[2:0] = 000 BSHW1[3:0] = 0000 WS RGB 1 = 000 : black BSW1=0 HSW1[4:0] = 25 (26 characters) VSW1[3:0] = 11 (12 rows of characters) T1 = 0 RGB W1 = 111:white RST = 0
HDW2[6:0] = 32 VDW2[5:0] = 0 BSWW2[2:0] = 000 BSHW2[3:0] = 0000 WS RGB 2 = 000 : black BSW2=0 HSW2[4:0] = 9 (10 characters) VSW2[3:0] =4 (5 rows of characters) T2 = 0 HDW3[6:0] = 0 VDW3[5:0] =12 BSWW3[2:0] = 000 BSHW3[3:0] = 0000 WS RGB 3 = 000 : black BSW3=0 HSW3[4:0] = 15 (16 characters) VSW3[3:0] = 7 (8 rows of characters) T3 = 0 RGB W3 = 111:white RGB W2 = 111:white
HDW4[6:0] = 16 VDW4[5:0] = 12 BSWW4[2:0] = 000 BSHW4[3:0] = 0000 WS RGB 4 = 000 : black BSW4=0 HSW4[4:0] = 15 (16 characters) VSW4[3:0] = 7 (8 rows of characters) T4 = 0 RGB W4 = 111:white
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Registers
Table 49: Control Registers: Window 0, Row = 1 FWR
81h 81h 81h 81h 81h 81h 81h 81h 81h 81h 81h 81h 81h 81h 81h 81h 81h 81h
STV9937
FAC
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 1xh 1Fh
Col Default
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 1xh 1Fh 50h 4h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h
Bit 7
0
Bit 6
THCTL = 1
Bit 5
CLP = 0
Bit 4
Bit 3
Bit 2
Bit 1
0
Bit 0
ENPB = 0
ENCL = 1 HFLYP = 0 OSDREF = 0 0 1
PBVM = 0 PBON = 0
OFFSETLIN[1:0]
OFFSETPIX[5:0] X1[12:8] X1[7:0] X2[12:8] X2[7:0] Y1[10:8] Y1[7:0] Y2[10:8] Y2[7:0] D3A[7:0] D3B[7:0] D3C[7:0] Reserved Reserved Reserved
HMUX = 0
0
0
0
0
0
0
0
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STV9937
Table 50: Color Registers: Window 0, Row = 2 FWR
82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h 82h
Registers
FAC
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Col
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Bit 7
WINDOW1 WINDOW1 WINDOW1 WINDOW1 WINDOW1 WINDOW1 WINDOW1 WINDOW1 WINDOW2 WINDOW2 WINDOW2 WINDOW2 WINDOW2 WINDOW2 WINDOW2 WINDOW2 WINDOW3 WINDOW3 WINDOW3 WINDOW3 WINDOW3 WINDOW3 WINDOW3 WINDOW3 WINDOW4 WINDOW4 WINDOW4 WINDOW4 WINDOW4 WINDOW4 WINDOW4 WINDOW4
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Color-box 1: BC- BR-BG-BB-blink-FR-FG-FB Color-box 2: BC- BR-BG-BB-blink-FR-FG-FB Color-box 3: BC- BR-BG-BB-blink-FR-FG-FB Color-box 4: BC- BR-BG-BB-blink-FR-FG-FB Color-box 5: BC- BR-BG-BB-blink-FR-FG-FB Color-box 6: BC- BR-BG-BB-blink-FR-FG-FB Color-box 7: BC- BR-BG-BB-blink-FR-FG-FB Color-box 8: BC- BR-BG-BB-blink-FR-FG-FB Color-box 1: BC- BR-BG-BB-blink-FR-FG-FB Color-box 2: BC- BR-BG-BB-blink-FR-FG-FB Color-box 3: BC- BR-BG-BB-blink-FR-FG-FB Color-box 4: BC- BR-BG-BB-blink-FR-FG-FB Color-box 5: BC- BR-BG-BB-blink-FR-FG-FB Color-box 6: BC- BR-BG-BB-blink-FR-FG-FB Color-box 7: BC- BR-BG-BB-blink-FR-FG-FB Color-box 8: BC- BR-BG-BB-blink-FR-FG-FB Color-box 1: BC- BR-BG-BB-blink-FR-FG-FB Color-box 2: BC- BR-BG-BB-blink-FR-FG-FB Color-box 3: BC- BR-BG-BB-blink-FR-FG-FB Color-box 4: BC- BR-BG-BB-blink-FR-FG-FB Color-box 5: BC- BR-BG-BB-blink-FR-FG-FB Color-box 6: BC- BR-BG-BB-blink-FR-FG-FB Color-box 7: BC- BR-BG-BB-blink-FR-FG-FB Color-box 8: BC- BR-BG-BB-blink-FR-FG-FB Color-box 1: BC- BR-BG-BB-blink-FR-FG-FB Color-box 2: BC- BR-BG-BB-blink-FR-FG-FB Color-box 3: BC- BR-BG-BB-blink-FR-FG-FB Color-box 4: BC- BR-BG-BB-blink-FR-FG-FB Color-box 5: BC- BR-BG-BB-blink-FR-FG-FB Color-box 6: BC- BR-BG-BB-blink-FR-FG-FB Color-box 7: BC- BR-BG-BB-blink-FR-FG-FB Color-box 8: BC- BR-BG-BB-blink-FR-FG-FB
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Application Hints
STV9937
10
10.1
Application Hints
Software Hints
10.1.1 Programming Recommendations
1. Write a new allocation just before the RAM reset. 2. Write a new allocation at any time but take care of the window display. 3. When resetting the RAM and writing in it just after, write in the RAM respecting the same order as the reset: from the first to the last reset window, from the first window address (row 0, col 0) to the last, incrementing columns, then rows, then windows. 4. Define the window horizontal size prior to writing character and color codes in RAM. HSWI is used to compute the RAM address.
10.1.2 Examples of Programming
It is recommended to program the STV9937 in the following sequence:
Via RGB Video mode
set ENPB =1 send data via RGB Video: Y then X coordinates.
Via I2C mode
set ENPB =1, PBVM=1, PBON =0 send data via I2C: X and Y coordinates. set PBON =1
Changing the mode
set PBON = 0 change PBVM bit write new coordinates, then the PBON can be set to 1. Hard reset at power-up (following a power-up)
1. Write Window 0 registers to set the OSD parameters: write
VCO[1:0], horizontal resolution and vertical height of characters, the position of reference, the allocations if they are incorrect
(by default: 320 characters for window 1, 128 characters for each of the others windows)
the windows position and size, the color-boxes that will be used.
2. Write the character codes for each window to display. 3. Write the color-box data for each window to display. 4. Write the enable of windows: ENWi = 1 then ENOSD=1.
Change of position & size of 1 window (ex. window 3) without disable of window
1. Write new position and sizes. 2. Write new characters in the RAM.
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STV9937 Re-allocation, reset, and writing new characters in windows
1. Disable windows. 2. Write new allocations. 3. Reset the windows. 4. Write new positions and sizes in control registers. 5. Write new color-boxes. 6. Write new characters and color-box data. 7. Enable windows.
Application Hints
10.2
Hardware Hints
The serial resistors on the ROUT, GOUT, BOUT, FBLK and PB outputs must be as close as possible to the device. Both decoupling capacitors (100 nF and 100 F) must be as close as possible to the analog (pin 13) and digital (pin5) power supplies (see Figure 15). PLL network must be close to the device but far from the ROUT, GOUT, BOUT, FBLK and PB outputs. PLL network and ROUT, GOUT, BOUT and FBLK outputs should be separated by the AVDD 3.3 V power trace. PLL ground (AGND) should not be connected either to DVSS or to other grounds of the videoboard, as the ground is already connected internally. It is better to supply the STV9937 device through ferrite beads (as an example the ferrite bead could be 742 760 5 type from Wurth Electronik) instead of traditional inductance that could damage the OSD jitter with some parasitic resonance.

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Application Diagrams
STV9937
11
Application Diagrams
Figure 15: STV9937 Application Diagram
R35 9K1 U3 R3 3M3
1
C30 560pF R38 68K
AVSS RP VCO AVDD TEST 1 TEST 2 HFLY VS HSYNC SDA SCL nc
IVSS BIN GIN RIN IVDD DVDD DVSS PB BOUT GOUT ROUT FBLK
24 23
C32 100nF
2
C1 47pF 3.3V FB1 BEAD_COIL C34 100nF C35 100uF/25V
3 4 5 6
BLK/Hf ly R37 100R VS R39 100R HS R32 100R SDA R34 100R SCL
22
C33 100nF
From video connector
21
C38 100nF
3.3V FB2 BEAD_COIL C37 100uF/25V
20 19 18
R40 330R C36 100nF
7 8 9 10 11 12
17
R42 330R
16
R43 330R
15
R46 330R
To the pre-amplifier
14
R41 330R
13
STV9937
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STV9937
Electrical and Timing Characteristics
12
12.1
Electrical and Timing Characteristics
Absolute Maximum Ratings
Symbol Parameter
DC Supply Voltage Input Voltage for SCL, SDA, VS, HFLY and HSYNC Ambient Operating Temperature Storage Temperature
Value
-0.5, +4.0 -0.5, 5.5 0, +70 -40, +125
Unit
V V
o
AVDD, IVDD, DVDD, OVDD VIN TOPER TSTG
C
oC
12.2
Operating Conditions
Parameter
DC Supply Voltage AVDD, IVDD, DVDD, OVDD. Ambient Operating Temperature
Symbol
VDD TOPER
Min.
3.0 0
Typ.
3.3 25
Max.
3.6 70
Unit
V
oC
12.3
Electrical and Timing Characteristics
(VDD = 3.3V, VSS = 0V, TA = 0 to 70o, unless otherwise specified)
Symbol
Electrical Characteristics IDD VIL
Parameter
Min.
Typ.
Max.
Unit
Analog and Digital Supply Current AIDD+ DIDD + OIDD Input Low Voltage (SCL, SDA, VS, HFLY, HSYNC, TEST1 and TEST2 pins) RIN, GIN, BIN (Video Input Voltage Amplitude) 1 Input High Voltage (SCL, SDA, VS, HFLY and HSYNC pins) Test inputs are connected to ground RIN, GIN, BIN (Video Input Voltage Amplitude) 1 ROUT, GOUT, BOUT, FBLK and PB Output Low Voltage (IOL = 3 mA) 0 2.0 0.5 0.7
50 0.8 50 5.0 1.0 0.4 0.4 2.4 5.0
mA V mV V V V V V V
VIH
VOL SDA Open Drain Output Low Voltage (IOL = 4 mA) ROUT, GOUT, BOUT, FBLK and PB Output High Voltage (IOH = 3 mA) VOH SDA Open Drain Output High Voltage, pulled up by external 3V to 5V power supply
Timing Characteristics Freq (Hline) Horizontal Synchronization Input Range tr tf ROUT, GOUT, BOUT, FBLK and PB Output rise time (CLOAD = 15 pF) ROUT, GOUT, BOUT, FBLK and PB Output fall time (CLOAD = 15 pF) 2 2 150 kHz ns ns
1. For PictureBoost data transmission only
45/49
Electrical and Timing Characteristics
STV9937
12.4
IC Bus Characteristics
Table 51: Characteristics of the SDA an SCL bus lines for F/S-mode IC-bus devices Standard mode Fast mode Unit Min. Max. Min. Max.
Symbol
IC Interface: SDA and SCL tSP fSCL tHD;STA tLOW tHIGH tSU; tSTA tHD;DAT tSU;DAT tr tf tSU; tSTO tBUF Cb
Parameter
Pulse width of spikes which must be suppressed by the input filter SCL clock frequency Hold time (repeated) START Condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SCL and SDA signals Fall time of both SCL and SDA signals Set-up time for STOP condition Bus free time between a STOP and a START condition Capacitive load for each bus line
n/a 0 4.0 4.7 4.0 4.7 0 250
n/a 100
0 0 0.6 1.3 0.6 0.6
50 400
ns kHz s s s s
3.45
0 100
0.9
s ns
1000 300 4.0 4.7 400
20 + 0.1Cb 20 + 0.1Cb 0.6 1.3
300 300
ns ns s s
400
pF
Figure 16: Definition of Timing for F/S-modes
handbook, full page width
SDA tf
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL tHD;STA tSU;STA tSU;STO
S
tHD;DAT
tHIGH
Sr
P
S
46/49
STV9937
Package Mechanical Data
13
Package Mechanical Data
Figure 17: 24-Pin Plastic Dual In-Line Shrink Package
E E1
A1 A2
A
L Stand -o ff b b2 e eA eB
c D E
24
13 E1
0.15 in. 0.38 mm. Gage Plane
1
12 eC eB
Table 52: PDIP24S Package mm Dim. Min.
A A1 A2 b b2 c D E E1 e eA eB eC L N 0.00 2.54 3.30 0.51 3.05 0.38 0.89 0.23 22.35 7.62 6.10 6.40 1.78 7.62 10.92 1.52 3.81 24 0.000 0.100 0.130 3.30 0.46 1.02 0.25 22.61 4.57 0.56 1.14 0.38 22.86 8.64 6.86
inches Max.
5.08 0.020 0.120 0.015 0.035 0.009 0.880 0.300 0.240 0.252 0.070 0.300 0.430 0.060 0.150 0.130 0.018 0.040 0.010 0.890 0.180 0.022 0.045 0.015 0.900 0.340 0.270
Typ.
Min.
Typ.
Max.
0.200
Number of Pins
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Revision History
STV9937
14
Revision History
Table 53: Summary of Modifications Date Version
0.1 0.2 0.3 0.4 0.5 0.5 First Draft. General modifications, corrections and updates. Removal of draft status. Update to Figure 3: PictureBooSTTM System Block Diagram on page 6. Updated Section 10.2: Hardware Hints on page 43 and Figure 15: STV9937 Application Diagram on page 44. PLL synchronization information added.
Description
20 February 2003 22 May 2003 26 June 2003 08 July 2003 24 September 2003 20 January 2004
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STV9937
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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